Field of the Disclosure
The embodiments concern methods of manufacturing semiconductor devices using sampling plans as well as process control in semiconductor wafer processing.
Description of Related Art
In the course of manufacturing semiconductor elements, metrology tools monitor the results of process steps effective on wafers. Results of wafer metrology may be used for fault detection, for determining abnormal equipment states, for executing tool alarms, for examining the cause of faults and for classifying a process wafer as a faulty wafer or as a wafer in line with target tolerances. Feed forward control uses the results of previous inspections for adjusting process parameters of following processes. Run-to-run control automatically changes process recipe parameters for a given wafer or wafer lot on the basis of feed-back data from post-process metrology applied to a previous run. APC (advanced process control) combines aspects of fault detection, classification, feed forward control and run-to-run control. Metrology sites may include specially designed measurement targets and/or portions of a product pattern.
Wafer metrology aims at an economic trade-off between metrology costs and yield improvement. Typically, wafer metrology uses a sampling plan defining the position of a number of metrology sites on selected process wafers of a wafer lot and exclusively measures selected process wafers at the metrology sites identified in the sampling plan. The metrology sites may be within exposure fields, outside of the exposure fields, e.g., in a wafer edge area, within chip areas and/or outside of the chip areas, e.g., in kerf areas of a wafer.
Sampling plans may be changed inbetween successive lots of semiconductor wafers to adjust for a changed state of the exposure and processing equipment. US 2014/0354969 A1 assigns a plurality of substrates to different sub-sampling plans.
There is a need for improving the effectiveness of sampling plans and for increasing the efficiency of the sampling plans.